The present invention is directed, in general, to microprocessors and, more particularly, to a processor architecture employing an improved floating point unit (FPU) and a computer system employing the processor.
The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (xe2x80x9cI/Oxe2x80x9d) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions. The I/O devices are operative to interact with a user through a graphical user interface (xe2x80x9cGUIxe2x80x9d) (such as provided by Microsoft Windows(trademark) or IBM OS/2(trademark)), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor""s power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, there is a practical maximum to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (xe2x80x9cprocessor throughputxe2x80x9d). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a xe2x80x9cpipelinexe2x80x9d). Instructions are processed in an xe2x80x9cassembly linexe2x80x9d fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
xe2x80x9cSuperpipeliningxe2x80x9d extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is xe2x80x9csuperscalarxe2x80x9d processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (xe2x80x9cdegree of scalabilityxe2x80x9d). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (xe2x80x9cbubblesxe2x80x9d or xe2x80x9cstallsxe2x80x9d) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor""s architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized.
Statistically, certain instructions are executed more frequently than others. If the design of a processor is optimized to rapidly process the instructions which occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
As computer programs have become more graphic-oriented, processors have had to deal increasingly with the conversion between floating point and integer representations of numbers. Thus, to enhance the throughput of a processor that must generate data necessary to represent graphical images, it is desirable to optimize the processor to efficiently convert floating point data to integer data.
Therefore, what is needed in the art is an efficient system and method for converting numbers from floating point notation to integer notation and a computer system employing the same. Preferably, the optimization of the processor should not require any additional hardware or degrade the performance of the processor in performing tasks other than floating point to integer conversions.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an efficient system and method for converting numbers from floating point notation to integer notation and a computer system employing the system or the method.
In the attainment of the above primary object, the present invention provides, for use in a processor having integer and floating point execution cores, logic circuitry for, and a method of, converting negative numbers from floating point notation to integer notation. In one embodiment, the logic circuitry includes: (1) a shifter that receives a number in floating point notation and shifts a fraction portion of the received number as a function of an exponent portion thereof to yield a shifted fraction portion and rounding data, (2) a one""s complementer, coupled to the shifter, that inverts the shifted fraction portion to yield an unincremented inverted shifted fraction portion, (3) an incrementer, coupled to the one""s complementer, that increments the unincremented inverted shifted fraction portion to yield an incremented inverted shifted fraction portion and (4) a multiplexer, coupled to the one""s complementer and the incrementer, that selects one of the unincremented inverted shifted fraction portion and the incremented inverted shifted fraction portion based on the rounding data thereby to yield the received number in integer notation.
The present invention therefore fundamentally reorders the process by which numbers are converted from floating point to integer notation to allow such numbers to be converted faster (typically expressed in terms of clock cycles) and, in some embodiments, as a pipelined process. The present invention is founded upon the novel realization that the two""s complement of a rounded-up, negative floating point number is equivalent to the one""s complement of the number.
In one embodiment of the present invention, the logic circuitry further includes a second multiplexer, interposed between the one""s complementer and the incrementer, that selects one of the shifted fraction portion and the inverted shifted fraction portion based on a sign of the received number. Thus, the present invention can be adapted for use in additionally converting positive numbers. Positive numbers have no need to be two""s complemented during conversion. Therefore, in this embodiment, steps are taken to bypass the one""s complementing and incrementing to which negative numbers are subjected.
In one embodiment of the present invention, the logic circuitry further includes rounding logic, coupled to the shifter, that receives the rounding data and derives therefrom a rounding indicator (which may be a binary value). The multiplexer selects the one of the unincremented inverted shifted fraction portion and the incremented inverted shifted fraction portion based on the rounding indicator. In an embodiment to be illustrated and described, the present invention makes use of existing rounding logic to determine when rounding should or should not take place. In the embodiment, much of the conversion process takes place while the rounding logic derives the rounding indicator.
In one embodiment of the present invention, the logic circuitry further includes an exclusive OR gate that receives the rounding indicator and a sign of the number and causes the multiplexer to select the incremented inverted shifted fraction portion when the rounding indicator and the sign are at different logic levels. In this embodiment, the incremented inverted shifted fraction portion is properly selectable only when the rounding indicator and the sign are at different logic levels (incrementing should occur if the number is positive and requires upward rounding or if the number is negative and does not require upward rounding).
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.